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X9313
Digitally Controlled Potentiometer (XDCPTM)
Data Sheet April 18, 2007 FN8177.5
Linear, 32 Taps, 3 Wire Interface, Terminal Voltages VCC
The Intersil X9313 is a digitally controlled potentiometer (XDCP). The device consists of a resistor array, wiper switches, a control section, and nonvolatile memory. The wiper position is controlled by a 3-wire interface. The potentiometer is implemented by a resistor array composed of 31 resistive elements and a wiper switching network. Between each element and at either end are tap points accessible to the wiper terminal. The position of the wiper element is controlled by the CS, U/D, and INC inputs. The position of the wiper can be stored in nonvolatile memory and then be recalled upon a subsequent power-up operation. The device can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including: * Control * Parameter adjustments * Signal processing
Features
* Solid-state potentiometer * 3-wire serial interface * 32 wiper tap points - Wiper position stored in nonvolatile memory and recalled on power-up * 31 resistive elements - Temperature compensated - End to end resistance range 20% - Terminal voltages, -VCC to +VCC * Low power CMOS - VCC = 3V or 5V - Active current, 3mA max. - Standby current, 500A max. * High reliability - Endurance, 100,000 data changes per bit - Register data retention, 100 years * RTOTAL values = 1k, 10k, 50k * Packages - 8 Ld SOIC, 8 Ld MSOP and 8 Ld PDIP * Pb-free plus anneal available (RoHS compliant)
Block Diagram
DECODER U/D INC CS 5-BIT UP/DOWN COUNTER 31 30 29 5-BIT NONVOLATILE MEMORY 28 ONE OF THIRTY-TWO OUTPUTS ACTIVE AT A TIME 2 VSS (GROUND) VCC VSS GENERAL STORE AND RECALL CONTROL CIRCUITRY 1 0 RL/VL RW/VW DETAILED RH/VH
VCC (SUPPLY VOLTAGE)
UP/DOWN (U/D) INCREMENT (INC) DEVICE SELECT (CS) CONTROL AND MEMORY
RH/VH
RW/VW
TRANSFER GATES
RESISTOR ARRAY
RL/VL
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X9313 Ordering Information
PART NUMBER X9313UMI X9313UMIZ (Note) X9313UP X9313US* X9313USZ* (Note) X9313USI X9313USIZ (Note) X9313WMZ (Note) X9313WMI* X9313WMIZ* (Note) X9313WP X9313WPZ-3 X9313WPI X9313WPIZ X9313WS*, ** X9313WSZ*, ** (Note) X9313WSI* X9313WSIZ* (Note) X9313ZM X9313ZMZ (Note) X9313ZMI*, ** X9313ZMIZ*, ** (Note) X9313ZP X9313ZPI X9313ZPIZ (Note) X9313ZS*, ** X9313ZSZ*, ** (Note) X9313ZSI* X9313ZSIZ* (Note) X9313UM-3T1 X9313UMZ-3T1 (Note) X9313UMI-3* X9313UMIZ-3* (Note) X9313US-3*, ** X9313USZ-3*, ** (Note) X9313WM-3* X9313WMZ-3* (Note) X9313WMI-3* PART MARKING 13UI DDB X9313UP X9313U X9313U Z X9313U I X9313U ZI DDF 13WI DDE X9313WP X9313WP ZD X9313WP I X9313WP ZI X9313WS X9313W Z X9313WS I X9313WS ZI 313Z DDJ 13ZI DDH X9313ZP X9313ZP I X9313ZP ZI X9313ZS X9313 Z X9313ZS I X9313ZS ZI 13UD DDD 13UE 13UEZ X9313U D X9313U ZD 13WD DDG 13WE 10 3 to 5.5 50 1 10 VCC RANGE (V) 4.5 to 5.5 RTOTAL (k) 50 TEMPERATURE RANGE (C) -40 to +85 -40 to +85 0 to +70 0 to +70 0 to +70 -40 to +85 -40 to +85 0 to +70 -40 to +85 -40 to +85 0 to +70 -40 to +85 -40 to +85 -40 to +85 0 to +70 0 to +70 -40 to +85 -40 to +85 0 to +70 0 to +70 -40 to +85 -40 to +85 0 to +70 -40 to +85 -40 to +85 0 to +70 0 to +70 -40 to +85 -40 to +85 0 to +70 0 to +70 -40 to +85 -40 to +85 0 to +70 0 to +70 0 to +70 0 to +70 -40 to +85 PACKAGE 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld PDIP 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld MSOP (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld PDIP 8 Ld PDIP*** (Pb-free) 8 Ld PDIP 8 Ld PDIP*** (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld PDIP 8 Ld PDIP 8 Ld PDIP*** (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) PKG. DWG. # M8.118 M8.118 MDP0031 MDP0027 M8.15 MDP0027 M8.15 M8.118 M8.118 M8.118 MDP0031 MDP0031 MDP0031 MDP0031 MDP0027 M8.15 MDP0027 M8.15 M8.118 M8.118 M8.118 M8.118 MDP0031 MDP0031 MDP0031 MDP0027 M8.15 MDP0027 M8.15
8 Ld MSOP Tape and Reel M8.118 8 Ld MSOP Tape and Reel M8.118 (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld MSOP M8.118 M8.118 MDP0027 M8.15 M8.118 M8.118 M8.118
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FN8177.5 April 18, 2007
X9313 Ordering Information (Continued)
PART NUMBER X9313WMIZ-3* (Note) X9313WS-3* X9313WSZ-3* (Note) X9313ZM-3* X9313ZMZ-3* (Note) X9313ZMI-3* X9313ZMIZ-3* (Note) X9313ZP-3 X9313ZPZ-3 (Note) X9313ZS-3* X9313ZSZ-3* (Note) X9313ZSI-3* X9313ZSIZ-3* (Note) PART MARKING 13WEZ X9313W D X9313W ZD 13ZD DDK 13ZE 13ZEZ X9313ZP D X9313ZP ZD X9313Z D X9313Z ZD X9313Z E X9313Z ZE 3 to 5.5 1 VCC RANGE (V) RTOTAL (k) TEMPERATURE RANGE (C) -40 to +85 0 to +70 0 to +70 0 to +70 0 to +70 -40 to +85 -40 to +85 0 to +70 0 to +70 0 to +70 0 to +70 -40 to +85 -40 to +85 PACKAGE 8 Ld MSOP (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld PDIP 8 Ld PDIP (Pb-free)*** 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) PKG. DWG. # M8.118 MDP0027 M8.15 M8.118 M8.118 M8.118 M8.118 MDP0031 MDP0031 MDP0027 M8.15 MDP0027 M8.15
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Add "T1" suffix for tape and reel. **Add "T2" suffix for tape and reel. ***Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
Pin Descriptions
RH/VH and RL/VL
The high (RH/VH) and low (RL/VL) terminals of the X9313 are equivalent to the fixed terminals of a mechanical potentiometer. The terminology of RL/VL and RH/VH references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and not the voltage potential on the terminal.
Chip Select (CS)
The device is selected when the CS input is LOW. The current counter value is stored in nonvolatile memory when CS is returned HIGH while the INC input is also HIGH. After the store operation is complete the X9313 will be placed in the low power standby mode until the device is selected once again.
Pinouts
X9313 8 LD PDIP, 8 LD SOIC TOP VIEW
INC U/D RH/VH VSS 1 2 X9313 3 4 6 5 8 7 VCC CS RL/VL RW/VW
RW/VW
RW/VW is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the control inputs. The wiper terminal series resistance is typically 40 at VCC = 5V.
Up/Down (U/D)
The U/D input controls the direction of the wiper movement and whether the counter is incremented or decremented.
X9313 8 LD MSOP TOP VIEW
RH/VH VSS RW/VW RL/VL 1 2 X9313 3 4 6 5 8 7 U/D INC VCC CS
Increment (INC)
The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or decrement the counter in the direction indicated by the logic level on the U/D input.
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FN8177.5 April 18, 2007
X9313
TABLE 1. PIN NAMES SYMBOL RH/VH RW/VW RL/VL VSS VCC U/D INC CS DESCRIPTION High terminal Wiper terminal Low terminal Ground Supply voltage Up/Down control input Increment control input Chip Select control input
The system may select the X9313, move the wiper and deselect the device without having to store the latest wiper position in nonvolatile memory. After the wiper movement is performed as described above and once the new position is reached, the system must keep INC LOW while taking CS HIGH. The new wiper position will be maintained until changed by the system or until a power-up/down cycle recalled the previously stored data. This procedure allows the system to always power-up to a preset value stored in nonvolatile memory; then during system operation minor adjustments could be made. The adjustments might be based on user preference, system parameter changes due to temperature drift, etc. The state of U/D may be changed while CS remains LOW. This allows the host system to enable the device and then move the wiper up and down until the proper trim is attained.
TABLE 2. MODE SELECTION CS L L H H X L L L INC U/D H L X X X H L Wiper up Wiper down Store wiper position Standby current No store, return to standby Wiper up (not recommended) Wiper down (not recommended) MODE
Principles of Operation
There are three sections of the X9313: the input control, counter and decode section; the nonvolatile memory; and the resistor array. The input control section operates just like an up/down counter. The output of this counter is decoded to turn on a single electronic switch connecting a point on the resistor array to the wiper output. Under the proper conditions the contents of the counter can be stored in nonvolatile memory and retained for future use. The resistor array is comprised of 31 individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked to either extreme. The electronic switches on the device operate in a "make before break" mode when the wiper changes tap positions. If the wiper is moved several positions, multiple taps are connected to the wiper for tIW (INC to VW change). The RTOTAL value for the device can temporarily be reduced by a significant amount if the wiper is moved several positions. When the device is powered-down, the last wiper position stored will be maintained in the nonvolatile memory. When power is restored, the contents of the memory are recalled and the wiper is set to the value last stored.
Symbol Table
WAVEFORM INPUTS Must be steady May change from Low to High May change from High to Low Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance
Instructions and Programming
The INC, U/D and CS inputs control the movement of the wiper along the resistor array. With CS set LOW the device is selected and enabled to respond to the U/D and INC inputs. HIGH to LOW transitions on INC will increment or decrement (depending on the state of the U/D input) a seven bit counter. The output of this counter is decoded to select one of thirty-two wiper positions along the resistive array. The value of the counter is stored in nonvolatile memory whenever CS transitions HIGH while the INC input is also HIGH.
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FN8177.5 April 18, 2007
X9313
Absolute Maximum Ratings
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65C to +135C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage on CS, INC, U/D, and VCC with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V Voltage on VH, VL, VW with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to +7V V = |VH - VL|: X9313Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4V X9313W, X9313U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10V Lead Temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . . +300C IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.8mA ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) . . . 2.0kV Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . .200V
Recommended Operating Conditions
Temperature: Commercial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Supply Voltage (VCC): X9313 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V 10% X9313-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 5.5V Max Wiper current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4mA Power rating: RTOTAL 10k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10mW RTOTAL 1k. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16mW Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications
CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Potentiometer CharacteristicsOver recommended operating conditions unless otherwise stated.
LIMITS SYMBOL PARAMETER End-to-end resistance tolerance VVH VVL RW IW VH terminal voltage VL terminal voltage Wiper resistance Wiper current Noise (Note 5) Resolution Absolute linearity (Note 1) Relative linearity (Note 2) RTOTAL temperature coefficient (Note 5) Ratiometric temperature coefficient (Note 5) CH/CL/CW (Note 5) NOTES: 1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = (VW(n)(actual) - VW(n)(expected)) = 1 MI maximum. 2. Relative linearity is a measure of the error in step size between taps = RW(n+1) - (RW(n) + MI) = 0.2 MI. 3. 1 MI = minimum increment = RTOT/31. Potentiometer capacitances See Circuit #3 RW(n)(actual) - RW(n)(expected) RW(n+1) - (RW(n)+MI) 300 20 10/10/25 Ref: 1kHz -120 3 1 0.2 IW = (VH - VL)/RTOTAL, VCC = 5V -VCC -VCC 40 TEST CONDITIONS/NOTES MIN TYP MAX 20 +VCC +VCC 100 4.4 UNIT % V V mA dBV % MI (Note 3) MI (Note 3) ppm/C ppm/C pF
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FN8177.5 April 18, 2007
X9313
DC Operating Characteristics Over recommended operating conditions unless otherwise stated.
LIMITS SYMBOL ICC ISB ILI VIH VIL CIN (Note 5) PARAMETER VCC active current Standby supply current CS, INC, U/D input leakage current CS, INC, U/D input HIGH current CS, INC, U/D input LOW current CS, INC, U/D input capacitance VCC = 5V, VIN = VSS, TA = +25C, f = 1MHz 10 TEST CONDITIONS/NOTES CS = VIL, U/D = VIL or VIH and INC = 0.42/2.4V @ max tCYC CS = VCC - 0.3V, U/D and INC = VSS or VCC - 0.3V VIN = VSS to VCC 2 +0.8 MIN TYP (Note 4) 1 200 MAX 3 500 10 UNIT mA A A V V pF
Endurance and Data Retention
PARAMETER Minimum endurance Data retention MIN 100,000 100 UNIT Data changes per bit per register Years
VH/RH
VH/RH TEST POINT RH CH
RTOTAL CW 25pF 10pF RW CL 10pF RL
VS
TEST POINT VW/RW VL/RL VL/RL
VW VW/RW FORCE CURRENT
FIGURE 1. TEST CIRCUIT #1
FIGURE 2. TEST CIRCUIT #2
FIGURE 3. CIRCUIT #3 SPICE MACRO MODEL
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FN8177.5 April 18, 2007
X9313
AC Operating Characteristics Over recommended operating conditions unless otherwise stated.
LIMITS SYMBOL tCI tID tDI tIL tIH tIC tCPH tCPH tIW tCYC tR, tF (Note 5) tPU (Note 5) tR VCC (Note 5) tWR (Note 5) NOTES: 4. Typical values are for TA = +25C and nominal supply voltage. 5. This parameter is not 100% tested. CS to INC setup INC HIGH to U/D change U/D to INC setup INC LOW period INC HIGH period INC inactive to CS inactive CS deselect time (STORE) CS deselect time (NO STORE) INC to VW change INC cycle time INC input rise and fall time Power-up to wiper stable VCC power-up rate Store cycle 0.2 10 10 50 2 500 PARAMETER MIN 100 100 2.9 1 1 1 20 100 5 TYP (Note 4) MAX UNIT ns ns s s s s ms ns s s s s V/ms ms
Power-Up and Power-Down Requirements
The recommended power-up sequence is to apply VCC/VSS first, then the potentiometer voltages. During power-up, the data sheet parameters for the DCP do not fully apply until
CS
1ms after VCC reaches its final value. The VCC ramp spec is always in effect. In order to prevent unwanted tap position changes, or an inadvertent store, bring the CS and INC high before or concurrently with the VCC pin on power-up.
tCYC tCI INC tIL tIH tIC tCPH 90% 10% tID U/D tDI tF tR 90%
tIW MI VW NOTE: MI IN THE AC TIMING DIAGRAM REFERS TO THE MINIMUM INCREMENTAL CHANGE IN THE VW OUTPUT DUE TO A CHANGE IN THE WIPER POSITION. (SEE NOTE)
FIGURE 4. AC TIMING DIAGRAM
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FN8177.5 April 18, 2007
X9313 Applications Information
Electronic digitally controlled potentiometers (XDCP) provide three powerful application advantages; (1) the variability and reliability of a solid-state potentiometer, (2) the flexibility of computer-based digital controls, and (3) the retentivity of nonvolatile memory used for the storage of multiple potentiometer settings or data.
Basic Configurations of Electronic Potentiometers
VR VH VW/RW VR
VL I THREE-TERMINAL POTENTIOMETER; VARIABLE VOLTAGE DIVIDER
TWO-TERMINAL VARIABLE RESISTOR; VARIABLE CURRENT
Basic Circuits
BUFFERED REFERENCE VOLTAGE R1 +V +5V VW VREF + - -5V R1 VOUT = VW/RW (a) (b) VO = (1 + R2/R1)VS VW - OP-07 VOUT +V VW/RW X -5V CASCADING TECHNIQUES +V +V VS + NONINVERTING AMPLIFIER +5V LM308A VO
R2
VOLTAGE REGULATOR
OFFSET VOLTAGE ADJUSTMENT R1 R2
COMPARATOR WITH HYSTERESIS
VIN
317 R1
VO (REG)
VS 100k - + VO
VS
LT311A
- + VO
}
}
Iadj R2 10k 10k VO (REG) = 1.25V (1 + R2/R1) + IADJ R2 +12V -12V 10k
TL072
R1
R2
VUL = [R1/(R1 + R2)] VO(max) VLL = [R1/(R1 + R2)] VO(min)
(FOR ADDITIONAL CIRCUITS SEE AN115)
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FN8177.5 April 18, 2007
X9313 Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1 -BE
INCHES SYMBOL A
ABC
MILLIMETERS MIN 0.94 0.05 0.75 0.25 0.09 2.95 2.95 4.75 0.40 8 0.07 0.07 5o 0o 15o 6o MAX 1.10 0.15 0.95 0.36 0.20 3.05 3.05 5.05 0.70 NOTES 9 3 4 6 7 Rev. 2 01/03
MIN 0.037 0.002 0.030 0.010 0.004 0.116 0.116 0.187 0.016 8 0.003 0.003 5o 0o
MAX 0.043 0.006 0.037 0.014 0.008 0.120 0.120 0.199 0.028
INDEX AREA
12 TOP VIEW
0.20 (0.008)
A1 A2
4X
0.25 (0.010) GAUGE PLANE SEATING PLANE -C-
R1 R
b c D E1
A
A2
4X
L L1
e E L L1 N R
0.026 BSC
0.65 BSC
A1
-He D
b
0.10 (0.004) -A0.20 (0.008)
C
SEATING PLANE
0.037 REF
0.95 REF
C a C L E1
C
R1 0
SIDE VIEW
15o 6o
-B-
0.20 (0.008)
CD
END VIEW
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension "D" does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (0.004) at seating Plane. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B - to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
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FN8177.5 April 18, 2007
X9313 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45 H 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.25 0.40 8 8 0 8 MAX 1.75 0.25 0.51 0.25 5.00 4.00 6.20 0.50 1.27 NOTES 9 3 4 5 6 7 Rev. 1 6/05
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 0.2284 0.0099 0.016 8 0
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 0.2440 0.0196 0.050
B C D E e H
C
A1 0.10(0.004)
0.050 BSC
1.27 BSC
e
B 0.25(0.010) M C AM BS
h L N
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
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FN8177.5 April 18, 2007
X9313 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. M 2/07
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FN8177.5 April 18, 2007
X9313 Plastic Dual-In-Line Packages (PDIP)
D E N PIN #1 INDEX
SEATING PLANE L e b
A2
A c
E1
A1 NOTE 5
eA eB
1
2 b2
N/2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE INCHES SYMBOL A A1 A2 b b2 c D E E1 e eA eB L N NOTES: 1. Plastic or metal protrusions of 0.010" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured with the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. PDIP8 0.210 0.015 0.130 0.018 0.060 0.010 0.375 0.310 0.250 0.100 0.300 0.345 0.125 8 PDIP14 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 14 PDIP16 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 16 PDIP18 0.210 0.015 0.130 0.018 0.060 0.010 0.890 0.310 0.250 0.100 0.300 0.345 0.125 18 PDIP20 0.210 0.015 0.130 0.018 0.060 0.010 1.020 0.310 0.250 0.100 0.300 0.345 0.125 20 TOLERANCE MAX MIN 0.005 0.002 +0.010/-0.015 +0.004/-0.002 0.010 +0.015/-0.010 0.005 Basic Basic 0.025 0.010 Reference Rev. C 2/07 2 1 NOTES
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN8177.5 April 18, 2007

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